In general, fabricating process of semiconductor integrated circuits undergoes procedures of concept designs, basic designs, detailed designs, prototype/debugging, and design variations/mass productions. However, a degree of flexibility in countermeasures is relatively large in an initial process, but the degree of flexibility thereof is reduced as the process advances toward a post-process. On the other hand, a countermeasure cost of the fabrication process is relatively small in the initial process but the countermeasure cost thereof is increased as the process advances toward the post-process. Accordingly, the total process number can be reduced by placing weight on the initial process. Also in thermal designs of semiconductor integrated circuits, it is necessary to advance such a front loading for placing weight on the initial process.
With miniaturization of semiconductor integrated circuit components, ambient temperatures Ta of devices have been greatly influenced depending on arrangement of each heat-generating component on mounting substrates. Moreover, with high-density mounting on mounting substrates, there has also occurred a situation of thermally interfering between adjacent semiconductor integrated circuit components. Accordingly, for example, analyses to which Computational Fluid Dynamics (CFD) is applied have been required therefor, and therefore needs for a thermal resistance model necessary for the analyses have grown.
In order to predict temperatures of each part of semiconductor integrated circuits including junction temperatures with a high degree of precision, precise models of internal structures will certainly be required. For example, a high-precision model in consideration of internal structures of semiconductor integrated circuits has been proposed as an analysis tool, and has been adopted by the Joint Electron Device Engineering Councils (JEDEC) which is a standard-setting organization.